Batch-based Design Rules Check
Our next step in the Design Process is to perform a Design Rule Check, more commonly known as DRC, on the layout. Although designers might be conscious of the design rules when performing the layout, there is a possibility of overlooking and thus violating the design rules. So, the DRC is a step taken to prompt us of any violations. This step is important because the violation of any design rules would result in a higher probability, and in some cases an absolute certainty, that the fabricated chip does not work as desired.
1. To run the DRC, choose DRC... from the Verify menu in the layout window.
- A pop up menu will appear. Just click on ok.
- You need to make sure that you're in edit mode for your layout that you
want to run DRC on.
Click on the OK button.
The CIW above shows that there are no errors found in the DRC process.
3. Let's perform a DRC on a layout that has errors...
The layout above shows the result of the DRC. Errors are indicated by the markers (white as shown above) but in your layout it will blink. The errors are also reported in the CIW as shown below.
4. You may then proceed to correcting the errors according to the design rules.
5. When performing huge layouts, the blinking marker might not be easily located at times. Fortunately, Cadence has an easy search tool. Under the Verify menu in the layout window, choose Markers → Find
- A pop up menu will appear. Click on the Zoom to
- Click on the Apply button and Cadence will zoom
in to the errors or warnings as desired.