Custom Layout Using Virtuoso
By now, you would have known how to enter and simulate your designs using Verilog-XL and Hspice. The next step in the process of making an integrated circuit chip is to perform a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices because it determines whether yours is a working design or not.
There are 2 ways to doing a layout: manual and automated. Manual layout usually enables the designer to pack his devices in a smaller area compared to the automated process but it is more tedious. The automated process, on the other hand, is done using standard cells and usually takes more real estate space but it is much faster. In this tutorial, you will learn how to perform manual layouts and a simple inverter layout will be shown.
Before we get into the layout, first you need to understand the design rules for layout. The design rules which we will be using is the MOSIS Scalable CMOS Rules. Design rules gives guidelines for generating layouts. They dictate spacings between wells, sizes of contacts, minimum spacing beween a poly and a metal and many other similar rules. Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. The design rules that we will be using can be obtained from the following link on MOSIS Layout Design Rules . Note that the layout is very much process dependent , since every process has a certain fixed number of available masks for layout and fabrication. For the case of this tutorial, we are using a AMI 1.5u CMOS process, which is a nwell process and supports two poly and two metal layers. Please make sure to click on SCNE when you access the above link for the design rules.
Before we proceed any further, please make sure that your present library is associated with a techfile. If you had followed this tutorial for your design of an inverter, then you might have already associated a techfile when you created a library ee560 in the first place. Otherwise, you can still do it, by clicking on the middle button by placing the mouse on the library name in the library manager window. There is an option for "Attach Tech Library". Once you choose that option, click on AMI 1.6u ABN(2P,NPN) as your process.
1. Create a layout cellview of the cell. Here we will create a layout
for the inverter cell.
In the library manager windown, click on the File → New → CellView. Choose CellName as
inverter and View Name as layout. Then click on the OK button. An empty Layout editor window
will pop-up
alongwith a LSW window. The LSW window will show all the layers like
nwell, pwell, active etc. for the given process. An alternate way to open
the layout editor window, click on "Layout" in
the View window for inverter cell in the Library manager window. Then click on
File → Open.
If the LSW window is blank, then there is an error. ( Follow this link to solve the problem).
The LSW window should look something like this
If you don't see the above ( not necessary to be in the above order) you will need to set the mask layers manually. To do this, go to Edit → Set Valid Layers and select/deselect the masks. Make sure that you at least have the following masks in your LSW window.
nwell, nselect, pselect, nactive, pactive, poly, elec, metal1, metal2 (all
dg's)
and
metal1, metal2 (pn's)
3. Since we are using AMI 1.6u technology, we only have a nwell process to use. Thus the substrate will be p-substrate. So we can always assume that the background is a p-sub. Now we will create a PMOS transistor first. To do that we need an Nwell in which the PMOS transistor will be formed.
The green shaded rectangle is the Nwell layer, the
green Nselect and the orange Pselect. The numbers are the length
in um (micro meters). Therefore , for the
AMI 1.6u
technology , λ = 0.8u and 2*λ = 1.6u. The editor options have been
defaulted such that every cursor advancement corresponds to 0.4u or 1/4th the
2*λ feature size. The ruler shown above can be invoked by typing
k. It can be removed by typing capital K. They show the length in micrometers.
The LSW window will be used to draw the masks in the layout editor window. To draw a mask, say an Nwell, first choose the corresponding layer in the LSW window by clicking on the layer. Then move your cursor into the layout window where you want to draw the Nwell layer and type r and move your mouse. A yellow box will appear indicating the boundary of the Nwell mask. Just click on the left mouse button to draw the Nwell rectangle; we'll worry about the actual dimension later. To change the dimension of the rectangle, move your cursor to the side where you want to extend or shorten such that the side is highlighted and then type s. The side will move with your cursor.
4. Likewise draw the Nselect and Pselect layer as shown in the figure above.
5. The Pselect is where you are creating the PMOS transistor since this is where the p+ diffusion is going to be formed. Draw the Pactive layer on your layout as shown in the figure below. The orange shaded rectangle is the p+ active regions. The green shaded rectangle is the n+ active region. Next draw the poly1 to form the gate of the transistor. The size of the PMOS transistor shown below has w=6.4um and l=2.4um using the 1.6um CMOS technology since 1 λ is 0.8um.
6. Next we need to connect the active regions to metal lines so that they can be routed. The figure below shows that metal1 (blue line-shaded polygons) are connected to the active region by an active contact (ca.dg which is solid black). Remember that the design rule usually restricts the size of the contact to be 2λ * 2λ, which is 1.6u * 1.6u. The Nselect creates an n+ diffusion in the Nwell. This is the body pin of the PMOS transistor which should be tied to VDD. We'll touch on how to connect VDD later.
Also a point of thought usually is how mush distance there should be between all these strange looking polygons. That is governed by the design rules , the link for which is given at the website MOSIS Layout Design Rules . You must know these rules for e.g. contact size should always be 2 λ * 2 λ, rules for distance beween poly and active region, etc.
7. Next you can proceed to create the NMOS transistor but this time your NMOS needs to be created in the Nselect while the p+ diffusion of the NMOS is in the Pselect. The size of the NMOS chosen in this design has the same length as the PMOS (2.4um) but the width of the NMOS is choses as 3.2um. Note that since we are using a nwell technology, we don't need an explicit well ( the pwell ) since the background is a psubstrate. The figure below shows the inverter.
We have chosen to space the NMOS and the PMOS by the distance of 30um active -to - active distance for a 1.6um process. This region between the two transistors would be used for pin definitions and for routing signals from one cell to another. The more the distance between the NMOS and the PMOS transistor, the more connections can be routed and less problems to worry about in the future when designing big cells. However, a large distance may result in a non-optimum and a very big layout. But for the sake of learning, we would rather choose to go with a large distance of around 30um.
8. The gate of the transistors need to be connected to metal1 lines for it to be accessed. To do that you will be using a contact "cc.dg" to make a contact between an already overlapping metal1 and poly. Similarly we desire to then connect the metal1 to metal2 ( though it is not necessary) for pin connections. For this purpose, we will make a contact between a metal1 and a metal2 using a "via". There are two ways of doing this.
Method 1: Bring metal 1 and metal 2 to overlap each other and then draw a "via.dg" rectangle of 2λ * 2λ (which is 1.6u*1.6u for AMI 1.6u process). Similarly bring poly and metal together and then draw a "cc.dg" rectabgle of 2λ * 2 λ.
Method2 : There are some ready to use macros available for making contacts. To access a macro cell which has a poly-metal1 combo with a single contact, instantiate the cell " M1_P" ( note capital letters) from the library "NCSU_TechLib_ami16". Similary to access a metal1-metal2 combo with a via, instantiate the cell "M1_M2" from the NCSU_TechLib_ami16 library. This cells will appear as a black box. To see through the cell, type "Shift -f". This will make the cell visible. Remember that you cannot update this cell, sinc eit is a standard library cell.
The figure below shows the connection. The pink shaded
polygon with a black square at the centre and blue borderline is the M1_P
contact.The pink-shaded polygons are metal2 while the solid pink squares are
Vias.
9. For simulation purposes and standard cell design rules, it is
necessary to add the PIN, or pn, layer. They are identical in purpose to
the input/output and vdd!/gnd! pins in the schematic. Power and ground
rail pins should be declared as jumpers. Input/output pins should be in
metal2 while power rail pins should be in metal1. It would not be a bad
idea to label your pins with the text layer, but make sure to name the labels
the same as the pins and put them on top of the labeled wires. Click on
metal2.pn in the LSW window. Then press Ctrl-p in the layout editor window. A
window will pop up. Enter the name 'inp' for labeling input. Choose "Display pin
name " optiion and define the pin as input. Then click on left mouse button with
the cursor placed at the left top corner of the metal2 square to be labeled.
Then drag the mouse to the right bottom corner of the same metal2 square, to be
labeled. Click one more time inside the metal2 square to place the text. Do the
same steps for placing a "out" pin except for the fact that you declare the pin
as "output".
10. Next we want to label the vdd! and gnd! pins. To do this select the Metal1 pn pattern
which is just a blue rectangle outline with an X across. To draw the
labels, type Ctrl-P. A pop up menu will appear.
Type vdd! for the Terminal
Names field and select the I/O type as jumper. Then move your cursor to the starting point
of the label and click on the left mouse button. Move your cursor to size
the label and click on the left mouse button again. Likewise, label the
gnd! pin. The figure below shows the pin labels
for vdd! and gnd!
