The parasitic capacitances created according to how your layout is done at times might be critical in affecting the actual performance of your design. In order to get an idea of how the design would work from your layout, you should perform a post-layout simulation from the extracted view. The procedure is identical to that for simulating from the schematic view.
Our main aim here is to just obtain the netlist from Cadence in the spice format, so that we can run hspice on the UNIX prompt. This method is preferable for lab users and people who like to write the hspice code themselves. However, for all others you may as well want to use the complete Analog Artist Lab suite to perform your simulations (not for students taking courses).
1. Open up your extracted view in edit mode. Under Tools menu, choose Analog Artist.
This will open up a window like the one given above. Now follow the steps for simulation using HSPICE .